1. Introduction
A PCB is a printed circuit board. PCBs are a part of our everyday lives; Computers, Cellphones, Calculators, Wrist-watches and every electrical component we interact with on a daily basis.
This article is targeted at professionals who are familiar with Hardware design and have PCB design background.
2. Shaping the PCB
The most common shape for PCB is rectangle. Many people also prefer to have the corners rounded, as this decreases the possibility of edge-cracking. The shape of PCB highly depends on where you are going to place the board, and what your mechanical requirements are (the final box where the product is placed).
Usually, there are 4 big holes in the board, each hole in one corner. These holes are used to hold the board in place using a patch or a PCB holder. The diameter is more than 2 millimeters, and it is plated.
3. How many layers to use?
Now we get to the next step, how many layers should we use? This highly depends on the maximum frequency used in the design, how many components you have, whether you have Ball-Grid-Array components or not, and most important of all, how dense your design is.
For systems running up to 80 MHz, usually it’s ok to use 2 Layers, should it be possible to route the board doing so. Take C.E. Certification and FCC regulations in consideration. Most of the times, the require a maximum of -130dBm emission on public radio band (FM 80-108MHz). This can be problematic if you use a high-current clock operating between 40 to 80 MHz (The second harmonic would be between 80 to 160 MHz, which can easily violate these rules).
For systems running above 80MHz, it is very important to consider using more layers, (4 is good example).
There are 2 tactics in 4 layers:
- Top and bottom layers can be Ground and Power planes. The middle layers used for routing.
- Top and bottom layers used for signal, Middle layers used for planes
The first method has a very good signal quality, since signals are sandwiched between two power planes, and as a result, you will have minimum emission.
The second method can make routing easy, since you will not need a via (vertical interconnect access) for each pin, as the pin resides on the same signalling layer. Further more, the internal planes can have multiple islands, to cover all your power needs, reducing the via count even further. BUT this method can be very tricky, and it
is extremely important NOT TO break power planes under high-speed signal, as this can result into a return path loop, making unwanted emission more likely to occur.
Using more layers always results into better quality of product, but it will make it more expensive to develop, especially in the prototyping stage. (The difference between 2 layers prototype and 4-6 layers, can be as high as few hundred dollars).
The six-layer+ method is almost ideal. Using top and bottom layer as power-planes and internal layers for routing can prevent emission, increase resistance to noise and dramatically reduce design efforts, as there are more layers to use for routing. Impedance-matching can be done easily, and we will cover this section for high-speed signals.
4. Arranging layers for Impedance-matching
At this point I assume you dealing with a high-speed system which has SSTL, HSTL, LVDS, RSDS, GTL+, High-Speed TTL and other high-speed interconnections (USB HS, 2.5Gbps PCI-Express, etc.). These routings require special considerations. The lines require impedance-matching. For many beginners, this can be a questioning term. The difference between Impedance and Resistance is great. If you need resistance matching, you can easily use a resistor and be done with it.
Impedance matching, on the other hand, has got nothing to do with resistors. It depends on the Width of the track, the underside power-plane, whether is it Strip-Line (Surrounded between two power planes) or uStrip (which means has a power plane under it, but the other side is free, as in TopLayer or BottomLayer).
To achieve a certain impedance on a track, you should carefully select these parameters. Use an impedance calculator (search google) to find the correct values for width, height above the power-plane, and thickness of the metallic layer, to achieve the desired impedance (usually 50 or 75 ohms).
Be advised that a miss-matched impedance connection (especially on RF, High-Speed USB, SATA or PCI-Express, and memory lines such as SSTL or HSTL), and make the board fail without any obvious reasons. This will force you to go for the next prototype, without ever finding what caused the first prototype to fail.
5. Power-planing.
Power-islands are one the most important factors in a high-speed digital design. An FPGA or high-speed processor board with in-accurate power-planing can be very unstable. In early days, you could route power tracks a little wider than signal-tracks, and treated them like normal connections. Today, the story is different.
If you use and FPGAs or High-Speed processors, you should know that a great number of flip-flops are switching at any given moment in your system. Their switching causes a huge amount of current going back-and-forward through their power and ground pins. The ground-pins in this case can create ground-bounce if the amount of current (and especially the slew-rate) is high. I must remind you of the famous V=L. di/dt (Delta-Voltage equals inductance x current-rate). If you use a track (for instance) to route ground signal, you will have different voltages on each side of the track. It will be very funny to have +0.5V on one side of your ground, and -1V on the other side.
This will cause COMPLETE SYSTEM FAILURE. I remember experiencing this issue in early days, which forced me to question even the very basic physique rules I knew. Discovering this bug can be difficult, and even if discovered, you will have no choice but to create another prototype.
The same rule applies for power-plane two. You can easily have drops in certain tracks if you do not use a plane, or a large power-islands, to support your power voltage. Using a greater number of decoupling capacitors is highly recommended for high-speed and high-powered processors/FPGAs, near their power lines.
The RF section, and the power-supply switching sections needs special care for their ground-planes. Their islands should be isolated from the system ground-plane, and must have tracks connecting your switching island to system ground (the tracks should be large enough to have near-zero DC resistance, but not more). This is because switching and RF section, can create waves on ground-plane, which can create ground-bounce on your systems ground. You can search google on this subject if you need more explanation.
6. High-Speed differential Signals
Todays designs always have a high-speed differential connection. Examples are PCI-Express, High-Speed USB and SATA. For these lines, certain rules apply:
- There should not be any ground-plane split under these connections.
- Their impedance should be carefully matched.
- There should not be more than 2 millimeters difference in LENGTH for each connection.
- Connections should maintain the same distance between each other until they reach destination.
- There should not be any sharp corners. Avoid 45 degrees or 90 degrees. This may cause unwanted Capacitive coupling, or it can cause the are act a small antennas.
- Keep all other signals far from these lines. I recommend minimum 5 millimeters separation. This will reduce cross-talk.
I recommend using Strip-lines for these connections. But again, many Micro-Strip will do fine as well.
7. High-Speed single-ended connections
Dealing with high-speed single-ended connections can be challenging. Since they are not differential lines, any noise on these lines will affect their state, and will cause system failure. HSTL, SSTL and GTL+ are good examples. LVTTL should be treated as well.
When routing these lines, take these tips into consideration:
- Impedance-matching is a MUST for these connections.
- No ground-splits underneath these connections.
- Cross-talk should be minimized. This highly depends on the type of the connection. LVTTL is most prone to cross-talk, as they do not have terminating resistors. I recommend using SSTL or HSTL where possible.
- Quite lines should be kept away from busy connections. These lines usually are control-lines and any cross-talk can be catastrophic (Imagine a cross-talk on chip-select connection!).
- Sharp-corners are OK with these signals, since they mostly operate under 800MHz.
- Reducing the number of vias used for these connections. Maximum of 2 is recommended.
8. High-Speed Memory routing tactics
Memory routing is a different story. When dealing with DDR2+, QDR, RDRAM, XDR and other high-speed chips, certain VERY IMPORTANT rules apply:
- The Clock-Line should always be longer than RAS, CAS and Data lines. The clock signal should arrive later than each of the signals, otherwise there will be synchronization problems. Usually high-speed memory controller have a ‘Return-Clock’ which is the clock trace returned to the controller, so the controller can tell when exactly the clock signal was intercepted by the chip.
- Data lines should never cross any plane-splits, as these lines more active than any other connection in the system.
- DDR systems have especial termination requirements (Usually Voltage-Termination). This voltage which is half of the memories supply voltage, should be VERY STABLE, as this sections supplies the termination resistors at each line-end. This supply voltage should have proper power-planing and a lot of capacitor decoupling (10nF for each 4 lines I recommend).
Again, consult your manufacturers datasheet for more considerations.
We are done for now, and I hope this article helped make things more clear for you in high-speed PCB routing techniques. This article will continue in PCB Routing Tips and Tactics 2.